Wednesday, December 14, 2011

APTRANSCO Assistant Engineer Practice Questions

Microprocessors : 
1. Which interrupt has the highest priority?
a) INTR b) TRAP c) RST6.5
2. In 8085 name the 16 bit registers?
a) Stack pointer b) Program counter  c) a & b
3. Which of the following is hardware interrupts?
a) RST5.5, RST6.5, RST7.5 b) INTR, TRAP c) a & b
4. What is the RST for the TRAP?
a) RST5.5 b) RST4.5 c) RST4
5. What are level Triggering interrupts?
a) INTR&TRAP b)RST6.5&RST5.5 c)RST7.5&RST6.5
6. Which interrupt is not level sensitive in 8085?
a) RST6.5 is a raising edge-trigging interrupt. b) RST7.5 is a raising edge-trigging interrupt. c) a & b.
7. What are software interrupts?
a) RST 0 – 7 b) RST 5.5 – 7.5 c) INTR, TRAP
8. Which stack is used in 8085?
a) FIFO b) LIFO c) FILO
9.  Why 8085 processor is called an 8 bit processor?
a) Because 8085 processor has 8 bit ALU. b) Because 8085 processor has 8 bit data bus. c) a & b.
10. What is SIM?
a) Select Interrupt Mask b) Sorting Interrupt Mask c) Set Interrupt Mask.
11. RIM is used to check whether, ______
a) The write operation is done or not b) The interrupt is Masked or not c) a & b
12. What is meant by Maskable interrupts? a) An interrupt which can never be turned off. b) An interrupt that can be turned off by the programmer. c) none
13.  In 8086, Example for Non maskable interrupts are
a) Trap b) RST6.5 c) INTR
14. What does microprocessor speed depends on?
a) Clock b) Data bus width c) Address bus width
15. Can ROM be used as stack?
a) Yes b) No c) sometimes yes, sometimes no
16.  Which processor structure is pipelined?
a) all x80 processors b) all x85 processors c) all x86 processors
17. Address line for RST3 is?
a) 0020H b) 0028H c) 0018H
18. In 8086 the overflow flag is set when
a) The sum is more than 16 bits b) Signed numbers go out of their range after an arithmetic operation c) Carry and sign flags are set d) During subtraction
19. The advantage of memory mapped I/O over I/O mapped I/O is,
a) Faster b) Many instructions supporting memory mapped I/O c) Require a bigger address decoder d) All the above
20. BHE  of 8086 microprocessor signal is used to interface the
a) Even bank memory b) Odd bank memory c) I/O d) DMA
21. In 8086 microprocessor the following has the highest priority among all type interrupts.
a) NMI b) DIV 0 c) TYPE 255 d) OVER FLOW
22. In 8086 microprocessor one of the following statements is not true.
a) Coprocessor is interfaced in MAX mode b) Coprocessor is interfaced in MIN mode c) I/O can be interfaced in MAX / MIN mode d) Supports pipelining
23. 8088 microprocessor differs with 8086 microprocessor in
a) Data width on the output b) Address capability c) Support of coprocessor d) Support of MAX / MIN mode
24. Address line for TRAP is?
a) 0023H b) 0024H c) 0033H

ANSWERS:
1 C 1.2 C  1.3 C 1.4 B 1.5 B 1.6 B 1.7 A 1.8 B 1.9 A 1.10 C 1.11 B 1.12 B 1.13 A 1.14 C 1.15 B 1.16 C 1.17 C 1.18 B 1.19 D 1.20 B 1.21 A 1.22 B 1.23 A 1.24 B

Microcontroller :

1. The 8051 microcontroller is of ___pin package as a ______ processor.
a) 30, 1byte b) 20, 1 byte c) 40, 8 bit d) 40, 8 byte
2. The SP is of ___ wide register. And this may be defined anywhere in the ______.
a) 8 byte, on-chip 128 byte RAM. b) 8 bit, on chip 256 byte RAM. c) 16 bit, on-chip 128 byte ROM d) 8 bit, on chip 128 byte RAM.
3. After reset, SP register is initialized to address________.
a) 8H b) 9H c) 7H d) 6H
4. What is the address range of SFR Register bank?
a) 00H-77H b) 40H-80H c) 80H-7FH d) 80H-FFH
5. Which pin of port 3 is has an alternative function as write control signal for external data memory?
a) P3.8 b) P3.3 c) P3.6 d) P3.1
6. What is the Address (SFR) for TCON, SCON, SBUF, PCON and PSW respectively?
a) 88H, 98H, 99H, 87H, 0D0H. b) 98H, 99H, 87H, 88H, 0D0H c) 0D0H, 87H, 88H, 99H, 98H d) 87H, 88H, 0D0H, 98H, 99H
7. Match the following:
1) TCON ——–i) contains status information
2) SBUF ——–ii) timer / counter control register.
3) TMOD——– iii) idle bit, power down bit
4) PSW——– iv) serial data buffer for Tx and Rx.
5) PCON ——-v) timer/ counter modes of operation.
a) 1->ii, 2->iv, 3->v, 4->i, 5->iii.    b) 1->i, 2->v, 3->iv, 4->iii, 5->ii.      c) 1->v, 2->iii, 3->ii, 4->iv, 5->i.     d) 1->iii, 2->ii, 3->i, 4->v, 5->iv.
8. Which of the following is of bit operations? i) SP ii) P2 iii) TMOD iv) SBUF v) IP
a) ii, v only b) ii, iv, v only c) i, v only d) iii, ii only
9. Serial port interrupt is generated, if ____ bits are set
a) IE b) RI, IE c) IP, TI d) RI, TI
10. In 8051 which interrupt has highest priority?
a)IE1 b)TF0 c)IE0 d)TF1
11. Intel 8096 is of ___ bit microcontroller family called as ______.
a) 8, MCS51 b) 16, MCS51  c) 8, MCS96 d) 16, MCS96
12. 8096 has following features fill up the following, i) ____ Register file, ii) ____ I/O Ports iii) ____ architecture.
a) 256 byte, five 8bit, register to register    b) 256 byte, four 8bit, register to register    c) 232 byte, five 8bit, register to register   d) 232 byte, six 8 bit, register to register
13. How many synchronous and asynchronous modes are there in serial port of 8096?
a) 2, 2 respectively    b) 3,1 respectively     c) 1, 3 respectively     d) 1, 2 respectively
14. In 8096 we have _____interrupt sources and _______ interrupt vectors.
a) 18, 8 b) 21, 6 c) 21, 8 d) 16, 8
15. 8096 has ___ general purpose I/O ports, Port 2 includes ______ of the following
i) two quasi-bidirectional I/O lines  ii) two output lines iii) four input lines iv) open drain outputs
a) 4, i, iv         b) 6, ii, iii       c) 4, i,ii,iii       d) 6, i, ii, iv
16. 8096 write-protected mode, no code can write to memory address between __.
a) 2020 to 3FFFH b) 8000 to FFFFH c) 2000 to 3FFFH d) 2020 to 202FH
17. If the __ pin is ___ , then we have the option of using the ____ ROM or EPROM together with _____ memory and devices.
a) EA, high, internal, external b) EA, low, internal, external c) EA, high, external, internal d) EA, low, external, internal
18. In 8096, CCB bit 3 is ____.
a) write strobe mode select b) address valid strobe select c) bus width select d) Internal read control mode
19. In 8096, mode ____ of serial port are ___ modes commonly used for ____ communications.
a) 1, 8bit, single processor    b) 0, 7bit, multiple microcontroller c) 2, 9 bit, multiple processors  d) 3, 8 bit, multiple microcontroller
20. What is the function of watchdog timer?
a) The watchdog Timer is an external timer that resets the system if the software
fails to operate properly.
b) The watchdog Timer is an internal timer that sets the system if the software fails
to operate properly.
c) The watchdog Timer is an internal timer that resets the system if the software fails
to operate properly.
d) None of them
 
ANSWERS:
1 C  2 D  3 C  4 D  5 C  6 A  7 A 8 A 9 D  10 C  11 D  12 C  13 C  14 C  15 C   16 C 17 A  18 B 19 C  20 C

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