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Wednesday, November 3, 2010

SAIL MTT EXAM COMPUTER SCIENCE QUESTIONS


1. Tn a packet switching network, packets are routed from source to destination along a single path having two intermediate nodes. If the message size is 24 bytes and each packet contains a header of 3 bytes, then the optimum packet size is
(a)4
(b)6
(c)7
(d)9

2. Suppose the round trip propagation delay for a 10 Mbps Ethernet having 48-bit jamming signal is 46.4 micro seconds The minimum frame size is?
(a) 94
(b) 416
(c) 464
(d) 512

3. For which one of the following reasons does Internet Protocol (IP) use the time-to-live (TTL) field in the IP datagram header?
(a) Ensure packets reach destination within that time
(b) Discard packets that reach later than that time
(c) Prevent packets from looping indefinitely
(d) Limit the time for which a packet gets queued in intermediate routers

4. Station A uses 32 byte packets to transmit messages to Station B using a sliding window protocol. The round trip delay between A and B is 80 milliseconds and the bottleneck bandwidth on the path between Aand B is 128 kbps. What is the optimal window size that A should use?
(a) 20
(b) 40
(c) 160
(d) 320

5. Two computers C1and C2 are configured as follows.
C1has IP address 203. 197.2.53 and netmask 255.255. 128.0.
C2 has IP address 203.197.75.201 and netmask 255.255.192.0.
Which one of the following statements is true?
(a) C1 and C2 both assume they are on the same network
(b) C2 assumes Cl is on same network, but C1 assumes C2 is on a different network
(c) C1 assumes C2 is on same network, but C2 assumes C1 is on a different network
(d) C1 and C2 both assume they are on different networks

6. Station A needs to send a message consisting of 9 packets to Station B using a siding window (window size 3) and go-back-n error control strategy. All packets are ready and immediately available for
transmission. If every 5th packet that A transmits gets lost (but no acks from B ever get lost), then what is the number of packets that A will transmit for sending the message to B?
(a)12
(b)14
(c)16
(d)18

7. For the given connection of LANs by bridges, which one of the following choices represents the depth first traversal of the spanning tree of bridges?
(a) B1,B5,B3,B4,B2
(b) B1,B3,B5,B2,B4
(c) B1, B5, B2, B3, B4
(d) B1,B3,B4,B5,B2

8.The micro instructions stored in the control memory of a processor have a width of 26 bits. Each micro-instruction is divided into three fields: a micro-operation field of 13 bits, a next address field (X), and a MUX select field (Y). There are 8 status bits in the inputs of the MUX.

How many bits are there in the X and Y fields, and what is the size
of the control memory in number of words?
(a)10,3,1024
(b) 8, 5, 256
(c) 5, 8 , 2048
(d) 10, 3, 512

9. A hard disk with a transfer rate of 10 M bytes/second is constantly transferring data to memory using DMA. The processor runs at 600 MHz, and takes 300 and 900 clock cycles to initiate and complete DMA transfer respectively. If the size of the transfer is 20 Kbytes, what is the percentage of processor time consumed for the transfer operation?
(a)5.0%
(b)1.0%
(c)0.5%
(d) 0.1%

10. A 4-stage pipeline has the stage delays as 150, 120, 160 and 140 nanoseconds respectively. Registers that are used between the stages have a delay of 5 nanoseconds each. Assuming constant clocking rate, the total time taken to process 1000 data items on this pipeline will be
(a) 120.4 microseconds
(b) 160.5 microseconds
(c) 165.5 microseconds
(d) 590.0 microseconds

11. Which one of the following is true for a CPU having a single interrupt request line and a single interrupt grant line?
(a) Neither vectored interrupt nor multiple interrupting devices are possible
(b) Vectored interrupts are not possible but multiple interrupting devices are possible
(c) Vectored interrupts and multiple interrupting devices are both possible
(d) Vectored interrupt is possible but multiple interrupting devices are not possible

12. Normally user programs are prevented from handling 110 directly by I/O instructions in them. For CPUs having explicit I/O instructions, such I/O protection is ensured by having the I/O instructions privileged. In a CPU with memory mapped I/O, there is no explicit I/O instruction. Which one of the following is true for a CPU with memory mapped I/O?
(a) I/O protection is ensured by operating system routine(s)
(b)I/O protection is ensured by a hardware trap
(c) I/O protection is ensured during system configuration
(d) I/O protection is not possible

13. What is the swap space in the disk used for?
(a) Saving temporarily html pages
(b) Saving process data
(c) Storing the super-block
(d) Storing device drivers

14. Increasing the RAM of a computer typically improves performance because
(a) Virtual memory increases
(b) Larger RAMs are faster
(c) Fewer page faults occur
(d) Fewer segmentation faults occur

ANSWERS:

1 d
2 d
3 b
4 b
5 c
6 c
7 a
8 a
9 d
10 c
11 b
12 a
13 b
14 c

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